As technology node shrinks, low electrical resistance is required for interconnect structures of semiconductor devices for overcoming resistor-capacitor (RC) delay. Metal silicide is widely used as electrical contacts and leads of transistors, due to its low electrical resistance and high adhesion to silicon material. Problems arise, however, because continuous scaling in manufacturing presents significant challenges to silicide engineering for high performance devices such as complementary metal-oxide-semiconductor (CMOS) logic devices. One of such challenges is to reduce source/drain contact resistances of CMOS devices.
Conventional methods for forming a metal silicide layer include steps as shown in FIGS. 1-3. Referring to FIG. 1, there is provided a semiconductor substrate 10 having a transistor formed thereon. The transistor includes a gate structure 11 on the substrate 10, a sidewall spacer 12 surrounding the gate structure 11, a source region 10a, and a drain region. The gate structure 11 may include a gate dielectric layer and a gate electrode as known in the art.
Referring to FIG. 2, a metal layer 13 is formed on the transistor structure shown in FIG. 1. The metal layer 13 can be formed of materials depending on types of metal silicide to be formed. For example, if a corresponding metal silicide (e.g., layer 14 in FIG. 3) is titanium silicide or nickel silicide, the metal layer 13 may be formed of a material containing titanium element or nickel element.
FIG. 3 shows a metal silicide layer 14 formed by heating the transistor structure shown in FIG. 2. During heating, the metal layer 13 reacts with the silicon material of the gate structure 11, the source region 10a, and the drain region 10b, whereby forming the metal silicide layer 14 as shown in FIG. 3. Unreacted portion of the metal layer 13 is subsequently washed off by acid.
During formation of metal silicides, material thermal stability plays an important role. For example, structure recombination and phase transformation may occur during heating due to undesired thermal stability of a metal silicide. In addition, device shrinkage may reduce thermal stability of the metal silicide.
Existing solutions to enhance thermal stability include addition of platinum (Pt) element in the metal silicides. For PMOS transistors, when a metal silicide layer containing Pt is used, Schottky barrier height (SBH) may be reduced at the interface between the metal silicide layer and the silicon material, thereby reducing the contact resistance of the PMOS transistor. As for NMOS transistors, however, use of metal silicide layer containing Pt does not reduce contact resistance.
Thus, there is a need to overcome these and other problems of the prior art and to provide materials and methods of forming a metal silicide layer and/or NMOS transistors with reduced contact resistance.